1. Field of the Invention
The present invention relates to a semiconductor device and a method of an operation thereof. More particularly, the present invention relates to a ferroelectric memory device and a method of an operation thereof.
2. Description of Related Art
In recent years, attention has been paid to a memory using a ferroelectric substance. It is possible for the ferroelectric memory device to be used as a non-volatile memory because dielectric polarization resides (residual polarization) after the electric power is turned off, if the polarization directions are aligned in one direction by applying a voltage to the ferroelectric substance once, since the ferroelectric memory device stores information using spontaneous polarization of the ferroelectric substance.
Further, a conventional non-volatile memory requires a high voltage of more than 10 V when data is written, and further the writing speed is in the order of micro seconds. On the other hand, it is possible for the ferroelectric memory device to reverse polarization using only several volts V, and the reverse speed is in the order of nano-seconds. In this way, the ferroelectric memory device is expected to be a next generation non-volatile memory capable of performing a low-voltage/high-speed operation.
The ferroelectric memory device is formed of a memory cell composed of a MOS transistor and a ferroelectric capacitor. The structure of the conventional ferroelectric memory device and the operation thereof are explained.
FIG. 1 shows the structure of the conventional ferroelectric memory device. Here, one of a plurality of memory cells is shown representatively. A memory cell 1 is formed of a transistor 3 and a ferroelectric capacitor 5. A gate of the transistor 3 is connected with a word line WL, a source is connected with a bit line BL, and a drain is connected with one terminal of the ferroelectric capacitor 5. The other terminal of the ferroelectric capacitor 5 is connected with a plate line PL. Further, the bit line BL is connected with a sense amp 7. When data is written to the memory cell 1, the transistor 3 is selected by way of the word line WL. Further, 0 V is applied to the bit line BL, and a positive voltage is applied to the plate line PL; accordingly dielectric polarization of the ferroelectric capacitor 5 is aligned towards the first direction from the electrode of the capacitor 5 connected to the plate line PL to the electrode of the capacitor 5 connected to the drain of the transistor 3, and the data xe2x80x9c0xe2x80x9d is written to the memory cell 1 as a result. On the other hand, if a positive voltage is applied to the bit line BL, and 0 V is applied to the plate line PL, dielectric polarization of the ferroelectric capacitor 5 is aligned towards the second direction opposite to the first direction, and the data xe2x80x9c1xe2x80x9d is written to the memory cell 1 as a result. When data stored in the memory cell 1 is read out, the bit line BL is pre-charged to 0 V , for example, and a positive voltage is applied to the plate line PL. At this time, the data xe2x80x9c1xe2x80x9d is stored in the memory cell 1 if the ferroelectric capacitor 5 is polarized towards the second direction, and the direction of dielectric polarization is reversed. On the contrary, when the data xe2x80x9c0xe2x80x9d is stored in the memory cell 1, and the ferroelectric capacitor 5 is polarized towards the first direction, the direction of dielectric polarization is not changed. The change of the direction of this dielectric polarization is reflected in the change of the voltage of the bit line BL. Thus, an electrical potential of the bit line BL is not the same depending on whether data stored in the memory cell 1 is xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d Further, the change of the voltage of the bit line BL is sensed by the sense amp 7, and the data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is read out.
In the sense amp 7, a reference voltage Vref is required to determine if data read out from the memory cell 1 is xe2x80x9c0/1.xe2x80x9d In the conventional way, in order to obtain the reference voltage Vref, a technology has been proposed in which data in reverse is stored in a dummy data cell and data read from the cell. In this case, two transistors and two capacitors for storing complimentary data xe2x80x9c0/1xe2x80x9d per piece of information are required. This is defined as a transistor 2 capacitor (2T2C) type.
The change of the voltage of the bit line BL, when the data is read out from the memory cell 1, is caused by the change of a quantity of electric charge stored in a bit line capacitor CBL of the bit line BL. Here, an operation in which the conventional ferroelectric memory device is read out, is explained using FIG. 2.
FIG. 2 is a hysteresis property curve of the ferroelectric capacitor 5 shown in FIG. 1. Here, the slope of a straight line obliquely across the hysteresis curve indicates a bit line capacitor CBL. When data xe2x80x9c1xe2x80x9d is stored in the memory cell 1, the ferroelectric capacitor 5 is in a state A0. Here, when the predetermined voltage is applied to the plate line PL, the ferroelectric capacitor 5 transits to a state A1, and a voltage Va is detected in the bit line BL. On the other hand, when data xe2x80x9c0xe2x80x9d is stored in the memory cell 1, the ferroelectric capacitor 5 is in a state B0. Here, the predetermined voltage is applied to the plate line PL, the ferroelectric capacitor 5 transits to a state B1, and a voltage Vb is detected in the bit line BL. Therefore, a potential difference xcex94V which has to be sensed by the sense amp 7 is Vbxe2x88x92Va, and it is required that the potential difference xcex94V be as large as possible and scatter be as small as possible in order to read data precisely from the memory cell 1.
In the 2T2C type ferroelectric memory device, which has been fabricated for practical use, a read out operation as shown in FIG. 2 was performed.
Although the ferroelectric memory device appears to be superior with regard to operation speed and operation voltage, the 2T2C type has not been used widely for circuit integration. Thus, it has not attained the same level of use as the DRAM, which is the main device favored by designers at the present time. Accordingly, an 1T1C type ferroelectric memory device having a compact circuit fit for practical use has been anticipated.
However, in the conventional 1T1C type ferroelectric memory device, the character of the ferroelectric capacitor changes if the operation for reading out the data is performed repeatedly. In particular, there has been a possibility of reading out wrong data in the case that the reference voltage has been fixed. The following two facts have been known with regard to the change of the ferroelectric capacitor characteristics.
(1) A phenomenon (Fatigue: lassitude) in which the quantity of dielectric polarization of the ferroelectric substance is small if bipolar (two poles) pulses are applied repeatedly.
(2) A phenomenon (Imprint: impression) in which dielectric polarization is difficult to reverse if unipolar (one pole) pulses are applied to the ferro-dielectric capacitor repeatedly or a direct-current voltage is applied thereto continuously.
Pursuant to the phenomenon (1), in recent years, a ferro-dielectric material and an electrode material, which would hardly cause the fatigue phenomenon, have been researched and developed, and thus this problem is about to be resolved.
On the other hand, pursuant to the phenomenon (2), an effective means has not yet been found. In addition, it is required to guarantee operation at a temperature of 80xc2x0 C. in order to equip the ferro-dielectric memory device with a logic IC, for example, however, it has become obvious that an imprint has become noticeable under this temperature.
As shown in the foregoing, a deterioration of the characteristics by the imprint has been one of the main factors obstructing making the 1T1C type ferro electric memory device fit for practical use.
The present invention has been invented in the light of the above-mentioned problems; the purpose thereof is to provide a ferro-dielectric memory device, in which the deterioration of the characteristics by the imprint is prevented, and a method for operating the ferro-dielectric memory device in which the deterioration of the characteristics by the imprint is prevented.
In order to solve the above-mentioned object, in the production method of a semiconductor device of the present invention, so as to solve the above mentioned problems, the ferro-dielectric memory device is provided, in which there are included a plurality of memory cells for storing data by polarization of a ferroelectric capacitor; a bit line to which each of the memory cells is connected; a pre-charge circuit, which is connected to one terminal of the bit line through a fifth switch unit, for providing a pre-charge voltage to the bit line; a first sub-bit line being connected to the other terminal of the bit line through a first switch unit; a data line for transmitting data being read out from each of the memory cells and data being written in each of the memory cells; a second sub-bit line being connected to the data line by way of a second switch unit; and a sense amp unit to which the first sub-bit line and the second sub-bit line are connected. Further, such a sense amp unit is characterized in that there are included a latch type sense amp for detecting the voltage of the first sub-bit line and for latching the voltage of the first sub-bit line at a predetermined level determined by a reference voltage; a grounding circuit connecting the first sub-bit line to a ground; a second transferring circuit for transferring a voltage logical level of the second sub-bit line to the first sub-bit line; and a first transferring circuit for transferring a voltage logical level, which is the reverse of the voltage logical level of the second sub-bit line, to the first sub-bit line.